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INTEGRATED CIRCUITS
DATA SHEET
SAB9079HS Multistandard Picture-In-Picture (PIP) controller
Preliminary specification File under Integrated Circuits, IC02 2000 Jan 13
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
FEATURES * Suitable for single PIP, double window and multi PIP applications * Data formats 4 : 1 : 1 (all modes) and 4 : 2 : 2 (most modes) * Sample rate of 14 MHz, 720 Y*-pixels/line * Horizontal reduction factors 11 34, 23, 12, 13, 14 and 16 * Vertical reduction factors
1 , 1 , 1 1 2 3
SAB9079HS
GENERAL DESCRIPTION The SAB9079HS is a PIP controller for a multistandard application environment in combination with a multistandard decoder such as for example TDA8310, TDA9143 or TDA9321H. The SAB9079HS inserts one or two live video signals with reduced sizes into the main/display video signal. All video signals are expected to be analog baseband signals. The analog signals are stripped signals without sync. Therefore the luminance signal is referred to as Y*. The conversion into the digital environment and back is done on-chip as well as the internal clock generation. The SAB9079HS is suitable for single PIP, double window and multi PIP applications.
and
1
4
* PIP OSD for the sub channels displayed * Detection of PAL/NTSC with overrule bit * CTE/LTE like circuits in display part * Replay with definable auto increment, picture sample rate and picture number auto wrap * Programmable Y*UV to RGB conversion matrix with independent coefficients for NTSC and PAL sources * Display clock and synchronisation are derived from the main PLL * Three 8-bit Digital-to-Analog Converters (DACs) * Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit performance) with clamp circuit for each acquisition channel * Main and sub can write to the same VDRAM address spaces under certain conditions; the reduction factors should be the same * Y* and UV pedestals on the acquisition sides * Independent vertical filtering with 1 : 1 for UV and Y* at the display part. ORDERING INFORMATION TYPE NUMBER SAB9079HS
PACKAGE NAME SQFP128 DESCRIPTION plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.72 mm VERSION SOT387-3
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
QUICK REFERENCE DATA SYMBOL Supplies VDDD(C) VDDD(P) VDDA IDDD(C) IDDD(P) IDDA PLL fosc fsys oscillator frequency system frequency 3584 x HSYNC 1792 x HSYNC 896 x HSYNC 448 x HSYNC Bloop tjitter loop bandwidth short term stability damping factor jitter during 64 s - - - - - - - 56 28 14 7 4 - 0.7 digital supply voltage for the core digital supply voltage for the periphery analog supply voltage digital supply current for the core digital supply current for the periphery analog supply current 3.0 4.5 3.0 tbf tbf - 3.3 5.0 3.3 115 10 170 PARAMETER CONDITIONS MIN. TYP.
SAB9079HS
MAX.
UNIT
3.6 5.5 3.6 tbf tbf 210 - - - - - 4 -
V V V mA mA mA
MHz MHz MHz MHz kHz ns
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VDDA(SP) VDDA(MA) VDDA(MH) VDDA(SF) VSSA(MA) VSSA(MP) VSSA(SA) VSSA(SP) CAS VDDA(MF) 1 3 VDDA(MP) 4 10 VDDA(SA) 11 12 99 VDDA(SH) 100 102 91 RAS 92 93 78 70 SY SU SV Vbias(SA) Vref(T)(SA) Vref(B)(SA) SHSYNC SVSYNC 105 103 101 104 107 106 94 95 126 128 2 127 124 125 9 8 CLAMP AND ADC HORIZONTAL AND VERTICAL FILTER PLL AND CLOCK GENERATOR LINE MEMORY
BLOCK DIAGRAM
Philips Semiconductors
WE 77 40
handbook, full pagewidth
Multistandard Picture-In-Picture (PIP) controller
DT
AD8 to AD0 SC 51
DAO0 to DAO15
DAI0 to DAI15
VDDA(DA) VSSA(DA) 30 VDDD(P) 31 113
79 to 83, 41 to 46, 74 to 71 49, 50, 69, 67, 65, 61, 59, 57, 55, 53
39 to 32, 68, 66, 64, 60, 58, 56, 54, 52
VDRAM CONTROL AND (RE-)FORMATTING
DAC AND BUFFER
24 27 29 28 26 25
DY DU DV Vbias(DA) Vref(B)(DA) Vref(T)(DA)
DISPLAY CONTROL
19
DFB
4
MY MU MV Vbias(MA) Vref(T)(MA) Vref(B)(MA) MHSYNC MVSYNC
CLAMP AND ADC
HORIZONTAL AND VERTICAL FILTER
SAB9079HS
LINE MEMORY TEST CONTROL 84 n.c.
PLL AND CLOCK GENERATOR
LINE MEMORY
I2C-BUS CONTROL
21 PLL AND CLOCK GENERATOR 20
DVSYNC DHSYNC
15, 18, 22, 85, 88, 109, 122 VDDD(C1) to VDDD(C7)
16, 17, 23, 86, 87, 108, 123
13, 47, 63, 75, 90
14, 48, 62, 76, 89
98
112 111 110 97
114 115 116 117 6
5
96
121 120 119 118 7
Preliminary specification
VSSD(C1) to VSSD(C7)
VSSD(P1) VDDD(P1) TSEXT TCBD SDA TSMSB POR TMEXT TM0 TM1 TMCLK to to MGS386 TCBR TCBC A0 SCL TMMSB TSCLK TM2 TC VSSD(P5) VDDD(P5)
SAB9079HS
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
PINNING SYMBOL VDDA(MF) MV VSSA(MA) VDDA(MA) TMEXT TMMSB TMCLK MVSYNC MHSYNC VDDA(MP) VSSA(MP) VDDA(MH) VSSD(P1) VDDD(P1) VDDD(C1) VSSD(C1) VSSD(C2) VDDD(C2) DFB DHSYNC DVSYNC VDDD(C3) VSSD(C3) DY Vref(T)(DA) Vref(B)(DA) DU Vbias(DA) DV VSSA(DA) VDDA(DA) DAI7 DAI6 DAI5 DAI4 DAI3 DAI2 DAI1 DAI0 DT 2000 Jan 13 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O S I S S I O I I I S S S S S S S S S O O O S S O I/O I/O O I/O O S S I I I I I I I I O analog V input of main channel analog ground for main channel ADCs analog supply voltage for main channel ADCs (3.3 V) set main PLL input for external mode (CMOS levels) test main MSB output of PLL counter (CMOS levels) test clock main input (CMOS levels) DESCRIPTION analog supply voltage for main channel front-end (3.3 V)
SAB9079HS
vertical sync input for main channel (CMOS levels with hysteresis) horizontal sync input for main channel (CMOS levels with hysteresis) analog supply voltage for main channel PLL (3.3 V) analog ground for main channel PLL supply of main HSYNC input (5.0 V) digital ground 1 for periphery; note 1 digital supply voltage 1 for periphery (5.0 V); note 2 digital supply voltage 1 for core (3.3 V); note 3 digital ground 1 for core; note 4 digital ground 2 for core; note 4 digital supply voltage 2 for core (3.3 V); note 3 fast blanking control output (CMOS levels) horizontal sync output (CMOS levels) vertical sync output (CMOS levels) digital supply voltage 3 for core (3.3 V); note 3 digital ground 3 for core; note 4 analog Y* output of DAC analog top reference for DACs analog bottom reference for DACs analog U output of DAC analog voltage reference DACs analog V output of DAC analog ground for DACs analog supply voltage for DACs (3.3 V) memory input data bit 7 (CMOS levels) memory input data bit 6 (CMOS levels) memory input data bit 5 (CMOS levels) memory input data bit 4 (CMOS levels) memory input data bit 3 (CMOS levels) memory input data bit 2 (CMOS levels) memory input data bit 1 (CMOS levels) memory input data bit 0 (CMOS levels) memory data transfer (CMOS levels) 5
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SYMBOL DAO0 DAO1 DAO2 DAO3 DAO4 DAO5 VSSD(P2) VDDD(P2) DAO6 DAO7 SC DAI15 DAO15 DAI14 DAO14 DAI13 DAO13 DAI12 DAO12 DAI11 DAO11 VDDD(P3) VSSD(P3) DAI10 DAO10 DAI9 DAO9 DAI8 DAO8 CAS AD0 AD1 AD2 AD3 VSSD(P4) VDDD(P4) WE RAS AD8 AD7 AD6 2000 Jan 13 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 I/O O O O O O O S S O O O I O I O I O I O I O S S I O I O I O O O O O O S S O O O O O DESCRIPTION memory output data bit 0 (CMOS levels) memory output data bit 1 (CMOS levels) memory output data bit 2 (CMOS levels) memory output data bit 3 (CMOS levels) memory output data bit 4 (CMOS levels) memory output data bit 5 (CMOS levels) digital ground 2 for periphery; note 1 digital supply voltage 2 for periphery (5.0 V); note 2 memory output data bit 6 (CMOS levels) memory output data bit 7 (CMOS levels) memory shift clock output (CMOS levels) memory input data bit 15 (CMOS levels) memory output data bit 15 (CMOS levels) memory input data bit 14 (CMOS levels) memory output data bit 14 (CMOS levels) memory input data bit 13 (CMOS levels) memory output data bit 13 (CMOS levels) memory input data bit 12 (CMOS levels) memory output data bit 12 (CMOS levels) memory input data bit 11 (CMOS levels) memory output data bit 11 (CMOS levels) digital supply voltage 3 for periphery (5.0 V); note 2 digital ground 3 for periphery; note 1 memory input data bit 10 (CMOS levels) memory output data bit 10 (CMOS levels) memory input data bit 9 (CMOS levels) memory output data bit 9 (CMOS levels) memory input data bit 8 (CMOS levels) memory output data bit 8 (CMOS levels) memory column address strobe output (CMOS levels) memory address output bit 0 (CMOS levels) memory address output bit 1 (CMOS levels) memory address output bit 2 (CMOS levels) memory address output bit 3 (CMOS levels) digital ground 4 for periphery; note 1 digital supply voltage 4 for periphery (5.0 V); note 2 memory write enable output (CMOS levels) memory row address strobe output (CMOS levels) memory address output bit 8 (CMOS levels) memory address output bit 7 (CMOS levels) memory address output bit 6 (CMOS levels) 6
SAB9079HS
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SYMBOL AD5 AD4 n.c. VDDD(C4) VSSD(C4) VSSD(C5) VDDD(C5) VDDD(P5) VSSD(P5) VDDA(SH) VSSA(SP) VDDA(SP) SHSYNC SVSYNC TSCLK TSMSB TSEXT VDDA(SA) VSSA(SA) SV VDDA(SF) SU Vbias(SA) SY Vref(B)(SA) Vref(T)(SA) VSSD(C6) VDDD(C6) TCBC TCBD TCBR VDDD(P) A0 SDA SCL POR TC TM1 TM2 TM0 VDDD(C7) 2000 Jan 13 PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 I/O O O - S S S S S S S S S I I I O I S S I S I I/O I I/O I/O S S I I I S I I/O I I I I/O I/O I S DESCRIPTION memory address output bit 5 (CMOS levels) memory address output bit 4 (CMOS levels) not used in application digital supply voltage 4 for core (3.3 V); note 3 digital ground 4 for core; note 4 digital ground 5 for core; note 4 digital supply voltage 5 for core (3.3 V); note 3 digital supply voltage 5 for periphery (5.0 V); note 2 digital ground 5 for periphery; note 1 supply of sub HSYNC input (5.0 V) analog ground for sub channel PLL analog supply voltage for sub channel PLL (3.3 V)
SAB9079HS
horizontal sync input for sub channel (CMOS levels with hysteresis) vertical sync input for sub channel (CMOS levels with hysteresis) test clock input for sub (CMOS levels) test sub MSB output for PLL counter (CMOS levels) set sub PLL input for external mode (CMOS levels) analog supply voltage for sub channel ADCs (3.3 V) analog ground for sub channel ADCs analog V input of sub channel analog supply voltage for sub channel frontend (3.3 V) analog U input of sub channel analog bias reference input for sub channel ADCs analog Y* input of sub channel analog bottom reference for sub channel ADCs analog top reference for sub channel ADCs digital ground 6 for core; note 4 digital supply voltage 6 for core (3.3 V); note 3 test control block clock input (CMOS levels) test control block data input (CMOS levels) test control block reset input (CMOS levels) digital supply voltage for periphery (5.0 V); note 5 address select pin input (I2C-bus) (CMOS levels) serial input data/ACK output (I2C-bus) (CMOS input levels) serial clock input (I2C-bus) (CMOS levels) power-on reset input (CMOS levels with hysteresis and pull-up resistor to VDD) test control input (CMOS levels) test mode input/output (CMOS levels with hysteresis and pull-up resistor to VDD) test mode input/output (CMOS levels with hysteresis and pull-up resistor to VDD) test mode input (CMOS levels) digital supply voltage 7 for core (3.3 V); note 3 7
Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SYMBOL VSSD(C7) Vref(T)(MA) Vref(B)(MA) MY Vbias(MA) MU Notes 1. All periphery VSS(P) are internally connected to each other, unless otherwise specified. 2. All periphery VDD(P) are internally connected to each other, unless otherwise specified. 3. All core VDD(C) are internally connected to each other. 4. All core VSS(C) are internally connected to each other. 5. This pin is NOT connected to the other periphery VDD(P). PIN 123 124 125 126 127 128 I/O S I/O I/O I I/O I digital ground 7 for core; note 4 analog top reference for main channel ADCs analog bottom reference for main channel ADCs analog Y* input for main channel analog bias reference for main channel ADCs analog U input for main channel DESCRIPTION
SAB9079HS
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
handbook, full pagewidth
125 Vref(B)(MA) 124 Vref(T)(MA)
106 Vref(B)(SA)
107 Vref(T)(SA)
123 VSSD(C7) 122 VDDD(C7)
109 VDDD(C6)
108 VSSD(C6)
127 Vbias(MA) 126 MY
104 Vbias(SA)
113 VDDD(P)
112 TCBR
111 TCBD
110 TCBC
117 POR
115 SDA
121 TM0
120 TM2
119 TM1
116 SCL
128 MU
VDDA(MF) MV VSSA(MA) VDDA(MA) TMEXT TMMSB TMCLK MVSYNC MHSYNC
103 SU
102 VDDA(SF) 101 SV 100 VSSA(SA) 99 VDDA(SA) 98 TSEXT 97 TSMSB 96 TSCLK 95 SVSYNC 94 SHSYNC 93 VDDA(SP) 92 VSSA(SP) 91 VDDA(SH) 90 VSSD(P5) 89 VDDD(P5) 88 VDDD(C5) 87 VSSD(C5) 86 VSSD(C4) 85 VDDD(C4) 84 n.c. 83 AD4 82 AD5 81 AD6 80 AD7 79 AD8 78 RAS 77 WE 76 VDDD(P4) 75 VSSD(P4) 74 AD3 73 AD2 72 AD1 71 AD0 70 CAS 69 DAO8 68 DAI8 67 DAO9 66 DAI9 65 DAO10
1 2 3 4 5 6 7 8 9
VDDA(MP) 10 VSSA(MP) 11 VDDA(MH) 12 VSSD(P1) 13 VDDD(P1) 14 VDDD(C1) 15 VSSD(C1) 16 VSSD(C2) 17 VDDD(C2) 18 DFB 19 DHSYNC 20 DVSYNC 21 VDDD(C3) 22 VSSD(C3) 23 DY 24 Vref(T)(DA) 25 Vref(B)(DA) 26 DU 27 Vbias(DA) 28 DV 29 VSSA(DA) 30 VDDA(DA) 31 DAI7 32 DAI6 33 DAI5 34 DAI4 35 DAI3 36 DAI2 37 DAI1 38
SAB9079HS
DAI0 39
DT 40
DAO0 41
DAO1 42
DAO2 43
DAO3 44
DAO4 45
DAO5 46 VSSD(P2) 47 VDDD(P2) 48
DAO6 49
DAO7 50
SC 51
DAI15 52
DAO15 53
DAI14 54
DAO14 55
DAI13 56
DAO13 57
DAI12 58
DAO12 59
DAI11 60
DAO11 61
VDDD(P3) 62 VSSD(P3) 63
105 SY
118 TC
114 A0
DAI10 64
MGS387
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SYSTEM DESCRIPTION PIP modes
SAB9079HS
An overview of the general PIP modes is given in Figs 3, 4 and 5. These pictures do not refer to all possible modes the device can handle. These modes are guaranteed only when sufficient memory is available and enough time is available to fetch all data from the memory.
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SP-Small
MGD594
SP-Medium
MGD595
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SP-Large
handbook, halfpage
MGD596
DP
handbook, halfpage
MGD597
Twin-PIP
MGD598
Full Field Still Full Field Live
MGD587
Fig.3 PIP modes.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
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MGS388
MGS389
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MGS390
POP-Right
MGD589
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POP-Left
MGD588
POP-Double
MGD590
Fig.4 PIP modes (continued).
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
handbook, halfpage
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MP7
MGD591
MP8
MGD592
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Quatro
MGD584
MP9
MGD585
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MP16
MGD586
MP13
MGL925
Fig.5 PIP modes (continued).
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Acquisition window The acquisition window is 720 pixels. This is related to a 720 whole line of 896 pixels. So for PAL --------- x 64 s will be 896 acquired from the active video. For NTSC this will be 720 slightly less --------- x 63.5 s . 896 The vertical acquisition window is 228 lines for NTSC and 276 lines for PAL. Data will be acquired in a 4 : 2 : 2 format. The acquisition clock is 896 x HSYNC. Acquisition fine positioning All I2C-bus settings relate to the incoming HSYNC, whether this is a real HSYNC or a burstkey for horizontal positioning. The same applys for the incoming VSYNC for vertical positioning. The relationships between the acquisition window and the internal clamp pulse are illustrated in Fig.6. In an application the clamp pulse must be positioned, by the I2C-bus, between the HSYNC and the start of the active video of the incoming signal. Display window
SAB9079HS
The display window available for PIP pictures is also 720 pixels wide, related to a 896 pixels line. The vertical display window is 228 lines for NTSC and 276 lines for PAL. Background window The origin of the display window is referenced to the origin of the background window. The background area is 768 pixels wide. Vertically it is 238 lines for NTSC and 286 lines for PAL. Display fine positioning The I2C-bus defined fine positioning has relationships to the internal HSYNC and VSYNC as illustrated in Fig.7.
handbook, full pagewidth
CIPER
CIDEL
MAHFP
MAVFP
228/276 lines
720 pixels
MGS391
The grey area depicts the background.
Fig.6 Acquisition fine positioning.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
handbook, full pagewidth
BGHFP
BGVFP SDVFP
SDHFP MDVFP MDHFP
SUB CHANNEL
MAIN CHANNEL 238/286 lines
768 pixels
MGS392
The grey area depicts the background.
Fig.7 Display fine positioning.
YUV to RGB conversion matrix A YUV to RGB conversion matrix is available. The nine matrix coefficient values can be set by I2C-bus commands. Two sets can be defined; one for PAL and one for NTSC. The matrix must be switched on, otherwise a 1 : 1 conversion takes place and Y*, U and V will be unmodified. The conversion matrix is based on the following equations. All results (R, G and B) fall in the range from 0 to 1. Any results outside of this range will be clipped to the nearest end value. It should be noted that gamma correction is not applied as is common practice. The end of this section contains an example. Normalised Y, U and V (indicated by subscript `a') are given by the following four equations: 1. Ya = x x Ra + y x Ga + z x Ba 2. x + y + z = 1 3. Ua = Ba - Ya 4. Va = Ra - Ya
Absolute or discrete (indicated by subscript `d') values for Y, U and V are given by the following three equations: 1. Yd = 255 x Ya (V), Ya normalised (range 0 to 1) 2. Ua U d = 128 + 127 x ----------- , 1-z Ua normalised (range -1 to +1) Va V d = 128 + 127 x ----------- , 1-x Va normalised (range -1 to +1)
3.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
Absolute or discrete (indicated by subscript `d') values for R, G and B are given by the following three equations: 1. 2. 3. 255 R d = Y d + --------- x ( V d - 128 ) x ( 1 - x ) 127 255 z 255 x G d = Y d - --------- x -- x ( 1 - x ) x ( V d - 128 ) - --------- x -- x ( 1 - z ) x ( U d - 128 ) 127 y 127 y 255 B d = Y d + --------- x ( U d - 128 ) x ( 1 - z ) 127
The implementation of a matrix with 9 coefficients is shown in Table 1. Table 1 Matrix coefficients Yd COFACTOR: Yd ry = 1 gy = 1 by = 1 Ud Vd
YUV TO RGB MATRIX COEFFICIENTS R G B
COFACTOR: 2 x (Ud - 128) COFACTOR: 2 x (Vd - 128) ru = 0 255 z gu = - --------- x -- x ( 1 - z ) -254 y 255 bu = --------- x ( 1 - z ) 254 255 rv = --------- x ( 1 - x ) 254 255 x gv = - --------- x -- x ( 1 - x ) -254 y bv = 0
So, for example; R = ry x Yd + ru x 2 x (Ud - 128) + rv x 2 x (Vd - 128) Table 2 shows how the coefficients can be calculated for a specific case where x = 0.299, y = 0.587 and z = 0.114. Calculation of xv:y* 128 (rounded to the nearest integer), translates to a binary value. Calculation of xu:xv: translates to a binary value with the coefficients for the binary bits: -1, 12 14, 18, 116, 132, 164 1128 (LSB). Table 2 Coefficient calculation EXPRESSION 1 0 255 --------- x ( 1 - x ) 254 1 255 z - --------- x -- x ( 1 - z ) -254 y 255 x - --------- x -- x ( 1 - x ) -254 y 1 255 --------- x ( 1 - z ) 254 0 DECIMAL VALUE 1 0 0.704 1 -0.173 -0.358 1 0.889 0 BINARY VALUE 10000000 00000000 01011010 10000000 11101010 11010010 10000000 01110010 00000000
COEFFICIENT ry ru rv gy gu gv by bu bv
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
PLL phase shift compensation for VCR When a VCR is applied as source for the main channel, a large phase jump can appear when the VCR head switches to another field. Since this phenomenon occurs around the VSYNC, its effects can be compensated. A prediction mechanism generates a compensation window around the VSYNC. This window can be manipulated with two parameters; VsPre and VsPost. * VsPre sets the number of lines before the predicted VSYNC, where the compensation window will start * VsPost sets the number of lines after the actual VSYNC, where the compensation window will end. Table 3 S Table 4 I2C-bus slave receiver protocol SLAVE A SUB A DATA A DATA I2C-bus I2C-BUS CONTROL
SAB9079HS
The SAB9079HS is a slave receiver/transmitter. The protocols are given in Tables 3 and 5.
A
P
Description of Table 3 DESCRIPTION START condition acknowledge bit (generated by SAB9079HS) STOP condition slave address; the data transmission starts with the slave address byte SLV (2CH or 2EH); the LSB of the SLV byte is the R/W bit which is logic 0 in slave receiver mode sub address byte; the SUB byte indicates the sub address which has to be written; if more than one data byte is send (as above) the internal sub address counter is automatically incremented after each data byte data byte; the data byte is the actual data written to the sub address; the functions of each sub address are explained in the following Sections I2C-bus slave transmitter protocol SLAVE A DATA A DATA A DATA N P
SYMBOL S A P SLAVE SUB
DATA
Table 5 S Table 6
Description of Table 5 DESCRIPTION START condition acknowledge bit; after the SLV generated by the SAB9079HS; after the DATA generated by the master acknowledge not bit; given by the master after the last data byte STOP condition slave address; the data transmission starts with the slave address byte SLV (2DH or 2FH); the LSB of the SLV byte is the R/W bit which is logic 1 in slave transmitter mode data byte; this is put on the bus by SAB9079HS in an auto increment mode; if the master gives an acknowledge the next data byte is sent; if the SAB9079HS has sent all its data it starts again with the first data byte and the sequence is repeated; this continues until an acknowledge not is given by the master
SYMBOL S A N P SLAVE DATA
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
The SAB9079HS has 8 read/status registers. The last 7 registers are reserved for future purposes. Reading a reserved register will return zero values. The SAB9079HS has 192 write registers. Writing to a reserved register is not allowed. An overview of all write registers is given in Table 7. Table 7 Description of write registers PURPOSE display positioning and sizing of PIPs decoder settings acquisition control decoder and PLL settings reserved decoder and PLL settings replay settings border and colour settings OSD controls YUV to RGB conversion matrix settings extra decoder settings reserved OSD characters reserved
SUB ADDRESS RANGE 00H to 04H 05H to 11H 12H to 17H 18H to 1FH 20H to 25H 26H to 28H 29H to 2AH 2BH to 2FH 30H to 37H 38H to 3CH 3DH to 4EH 4FH to 5FH 60H to 7FH 80H to DFH E0H to FFH I2C-BUS READ REGISTERS
The SAB9079HS has 8 read/status registers. The register currently used are listed in Table 8. The remaining 7 are reserved for future purposes. Reading a reserved register will return zero values. Table 8 I2C-bus read registers DATA BYTES BIT 7 SNonInt BIT 6 Mask ID reserved reserved reserved reserved reserved reserved reserved BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SUB ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H
RepChano
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SNonInt
This bit indicates the internal interface status of the sub channel. A logic 0 indicates that the channel is in interlaced mode, a logic 1 indicates that the channel is non-interlaced.
SAB9079HS
* BGHfp, BGVfp, MDHfp, MDVfp, SDHfp and SDVfp * MHPic, MVPic, SHPic, SVPic, SHDis and SVDis * PIPGc,r * MHRed, MVRed, SHRed, SVRed, MLSel, SLSel and SBSel * OSDHfp, OSDVfp, OSDHDis and OSDVDis.
Mask ID
This bit gives the version number of the chip. A logic 0 indicates that a SAB9079N1 is used, a logic 1 indicates that a SAB9079N2 is used.
FillSet and FillOff
The FillSet bit sets the colour of all sub PIPs immediately to a 30% grey value if is set to logic 1. If FillSet is set to logic 0 then the 30% grey PIPs stay until the data in the VDRAM is updated (unfrozen). This bit should be used in the event that a new PIP mode is made in which the VDRAM data becomes invalid. FillOff works the opposite to FillSet. If this bit is set all the VDRAM data is made visible in the PIPs and no PIP has a grey content. This bit is generally not used.
RepChano
These bits indicate the present picture number, counting from 0, where replay acquisition is writing. I2C-BUS DISPLAY SETTING REGISTERS
MPIPON and SPIPON
If MPIPON is set to logic 1 (see Table 10) the main PIP is on. If it is set to logic 0 the main PIP is off. If SPIPON is set to logic 1 the sub PIPs are on, in accordance with the scheme of the PIPG bits (see Section "Positioning and sizing of PIPs"). If SPIPON is set to logic 0 all the sub PIPs are off. This can also be achieved by setting all PIPG bits to zero.
MiS
If the MiS bit is set to logic 0 the main and sub channels have their own independent memory spaces. If set to logic 1 the main and sub channels share the same memory space, this is only valid if the main and sub channels have the same reduction factors.
MFreeze and SFreeze
MFreeze and SFreeze control the writing of data to the VDRAM. If set to logic 0 the writing to the VDRAM is disabled after the next VSYNC. If set to logic 1 the writing is enabled after the next VSYNC.
YUVFilter
These bits control the vertical filtering of 1 : 1 for both the Y* and UV channels independently. Several display filter modes can be set with these bits. An overview is given in Table 9. The Y filter should not be used in vertical 11 modes. Table 9 Display filter modes MODE No filter UV 1 : 1 vertical filter Y 1 : 1 vertical filter YUV 1 : 1 vertical filter YUV FILTER 00H 01H 10H 11H
I2CHold
The I2C-bus hold bit is set to logic 0 (default). This means that all I2C-bus data is directly clocked into the internal registers. A part of the I2C-bus data will be clocked in on the next VSYNC (e.g. the reduction factors and the display positioning). If the I2CHold bit is logic 1 that part of the I2C-bus will not be clocked in on the next VSYNC. To make the data available the I2CHold bit should be set to logic 0 again. This function is useful when much data has to be sent and a screen update is not allowed when sending this data. A list of I2C-bus registers which are clocked in on a VSYNC is given below: * MPIPON and SPIPON * MFreeze, SFreeze and FillSet * DNonInt, MNonInt and SNonInt * PRIO
CTE and LTE
Colour Transient Enhancement (CTE) can be set on or off. Luminance Transient Enhancement (LTE) is controllable via a scale, setting the scale value to 0H means that LTE is off.
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
MFld and SFld
The number of fields stored in the VDRAM can be set with the MFld and SFld bits. There is a limit of 4 Mbits which can be stored. It is best to set these bits so that 3 fields are stored for the sub channel and 2 for the main channel, but this is not possible in all cases (large PIPs). Therefore, the number of fields stored can be reduced. This can result in some performance loss, e.g. if the sub channel is set to 1 field joint line errors can appear.
SAB9079HS
The xPal bits then determine the mode of the device. A logic 0 sets the device in NTSC mode, a logic 1 to PAL mode. DPAL overrules MPAL (main and display channels are coupled).
PRIO, NipCoff, Fmt411, DFilt and Yth
The PRIO bit sets the priority between the main and sub channels. A logic 0 gives priority to the sub channel which means that the sub channel PIPs, if present, are placed on top of the main PIP. A logic 1 places the main PIP on top of the sub PIPs. The NiPCoff bit determines whether a grey bar is inserted in case a NTSC PIP is displayed in a PIP with PAL PIP size. The missing lines are equally divided between the top part and the bottom part of the PIP window and made 30% grey. If this bit is logic 0 the grey bar is displayed, if this bit is logic 1 the grey bar is omitted and the PIP data is shifted up. The Fmt411 bit sets the YUV format. If this bit is logic 0 then the device is in 4 : 2 : 2 YUV mode, if this bit is logic 1 then the device is in 4 : 1 : 1 YUV mode. If the 4 : 2 : 2 format is used the memory use is larger, so some modes are not available and the length of a read/write cycle is larger. The Dfilt bit controls an interpolating filter to expand the internal 720 pixels data rate to the output data rate of 2 x 720 pixels in 1FH mode. If DFilt is logic 1 then the filter is on. The Yth(3 : 0) bits control the video output. If the current Y value is less then Yth x 16 then the fast blanking is switched off, and the original live background will be visible. This feature can be used to pick up sub-titles and display them as OSD anywhere on the screen.
IntOff, DNonInt, MNonInt and SNonInt
In automatic interlace mode (IntOff is logic 0) the device calculates whether interlaced or non-interlaced signals are applied and acts accordingly. This can be overruled by setting bit IntOff to logic 1. Bits DNonInt, MNonint and SNonInt then determine the interlace. If the xNonInt bits are set to logic 0 the device is put in interlaced mode, if they are set to logic 1 the main, sub and/or display channels are put in non-interlaced mode. DNonint overrules MNonint (main and display channels are coupled).
PalOff, DPal, MPal and SPal
In automatic mode (PalOff is logic 0) the device calculates what type of signal is applied, PAL or NTSC. In the event that the number of lines in a field is less than 287 it is assumed to be NTSC, otherwise it is assumed to be PAL. This can be overruled by setting PalOff to logic 1.
Table 10 overview of the I2C-bus sub addresses SUB ADDRESS 00H 01H 02H 03H 04H DATA BYTES BIT 7 MPIPON - IntOff PRIO BIT 6 SPIPON - DNonInt NipCoff BIT 5 MFreeze - - MNonInt Fmt411 BIT 4 SFreeze - - SNonInt DFilt BIT 3 I2CHold CTE Paloff DPal Yth(3 : 0) BIT 2 FillSet BIT 1 FillOff SFld(1 : 0) LTE(2 : 0) MPal SPal BIT 0 MiS
MFld(1 : 0)
YUVFilter(1 : 0)
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
POSITIONING AND SIZING OF PIPS The basic principle is the same as in the SAB9076/77. The only difference is that the main channel can only display 1 PIP. The algorithm for the sub channel is similar. The difference for the sub channel is that the number of PIPs for each row and the offset of the first PIP is replaced by grid bits. In the matrix of 16 PIPs every PIP can be put on or off. The I2C-bus registers are given in Table 11.
SAB9079HS
SHDis and SVDis
Bit SHDis controls the horizontal distance between the left sides of the sub PIPs on a row in steps of 4 pixels. Bit SVDis controls the vertical distance between the top lines of sub PIPs in steps of 1 line (both Pal and NTSC). The distances should always be equal or larger than the picture sizes so that the PIPs of one channel do not overlap. In the event of single PIP modes SHDis should be set to maximum.
BGHfp and BGVfp
The BGHfp and BGVfp bits control the horizontal (4 pixels/step) and vertical (2 line/field/step) background positioning (upper left corner).
MDHfp and MDVfp
The MDHfp and MDVfp bits control the horizontal and vertical main display positioning.
SDHfp and SDVfp
The SDHfp and SDVfp bits control the horizontal (4 pixels/step) and vertical (1 line/field/step) sub display positioning (upper left corner).
MHPic and MVPic
Bit MHPic controls the horizontal size of the main PIP in steps of 4 pixels (minimum is 24 pixels). Bit MVPic controls the vertical size of the main PIP in steps of 1 line/field for NTSC or 2 lines/field for PAL.
SHPic and SVPic
Bit SHPic controls the horizontal size of the sub PIP in steps of 4 pixels (minimum is 8 pixels). Bit SVPic controls the vertical size of the sub PIP in steps of 1 line/field for NTSC or 2 lines/field for PAL.
PIPGrow,col
The PIPGrow,col bits make it possible to set each individual PIP on or off in a multi PIP mode. PIPs are numbered according to Table 12. Rows are numbered from top to bottom, columns are numbered from left to right.
Table 11 I2C-bus registers for PIP SUB ADDRESS 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H PIPG1,3 PIPG3,3 PIPG1,2 PIPG3,2 PIPG1,1 PIPG3,1 DATA BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BGHfp(3 : 0) SDHfp(7 : 0) SDVfp(7 : 0) SHPic(7 : 0) SVPic(7 : 0) SHDis(7 : 0) SVDis(7 : 0) MDHfp(7 : 0) MDVfp(7 : 0) MHPic(7 : 0) MVPic(7 : 0) PIPG1,0 PIPG3,0 PIPG0,3 PIPG2,3
BGVfp(3 : 0)
PIPG0,2 PIPG2,2
PIPG0,1 PIPG2,1
PIPG0,0 PIPG2,0
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 12 PIP numbering ROW 0 1 2 3 ACQUISITION CONTROL Acquisition control sets the reduction factors, the acquisition fine positioning and the channel selection bits are given in Table 13. COLUMN 0 PIPG0,0 PIPG1,0 PIPG2,0 PIPG3,0 COLUMN 1 PIPG0,1 PIPG1,1 PIPG2,1 PIPG3,1 COLUMN 2 PIPG0,2 PIPG1,2 PIPG2,2 PIPG3,2
SAB9079HS
COLUMN 3 PIPG0,3 PIPG1,3 PIPG2,3 PIPG3,3
SLSel and MLSel
Bits SLSel and MLSel select which PIP is updated. A maximum of 16 PIPs can be displayed for the sub channel. The number counting is done from the left to right and from top to bottom. If all PIPs are on (see Table 12) 16 PIPs are displayed. If PIPs are put off the maximum number is limited to the number of PIPs displayed. In the PIP mode where the main and sub channel have the same reduction factors the main channel can write in sub VDRAM address spaces according to the same numbering. In all other cases MLSel is inoperative and should be set to 0H. For replay and other trick modes more PIPs can be stored and addressed via the higher numbers (17 to 60). The numbers 61, 62 and 63 are not valid.
SHRed, SVRed, MHRed and MVRed
The reduction factors can be set in accordance with Table 14.
SAHfp and SAVfp
The SAHfp and SAVfp bits control the horizontal (2 pixels/step) and vertical (1 line/field/step) sub acquisition positioning (upper left corner). When SAHfp is set to logic 0, the sub channel will enter the freeze mode.
MAHfp and MAVfp
The MAHfp and MAVfp bits control the horizontal (2 pixels/step) and vertical (1 line/field/step) main acquisition positioning (upper left corner). When MAHfp is set to logic 0, the main channel will enter the freeze mode. Table 13 Acquisition and channel selection bits SUB ADDRESS 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH - - - - DATA BYTES BIT 7 - - BIT 6 BIT 5 SVRed(2 : 0) MVRed(2 : 0) SAHfp(7 : 0) SAVfp(7 : 0) MAHfp(7 : 0) MAVfp(7 : 0) SLSel(5 : 0) MLSel(5 : 0) BIT 4 BIT 3 - - BIT 2 BIT 1 SHRed(2 : 0) MHRed(2 : 0) BIT 0
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 14 Reduction factors HORIZONTAL BITS MAIN 0H 1H 2H 3H 4H 5H 6H 7H DECODER AND PLL SETTINGS not valid
1 1 1 2 1 3 1 4 2 3 1 6 3 4
SAB9079HS
VERTICAL SUB not valid
1 1 1 2 1 3 1 4
MAIN not valid
1 1 1 2 1 3 1 4
SUB not valid
1 1 1 2 1 3 1 4
not valid
1 6
not valid not valid not valid
not valid not valid not valid
not valid
IntCoff, FbDel and YDel
Bit IntCoff sets the interlace correction. Interlace correction is put off if this bit is set to logic 1. FbDel(2 : 0) can adjust the fast blank delay in 8 steps of a 12 28 MHz clock cycle (-4 to +3); 0H is mid-scale. YDel adjusts the Y delay with respect to the UV delay; 0H is mid-scale from -4 to +3 pixels. YDel is done on the display side and therefore both channels, main and sub channels, will have an equal delay in the luminance.
SYClRef, SUClRef, SVClRef, MYClRef, MUClRef and MVClRef
The clamp reference level can be set separately for each of the 6 analog inputs; it acts as a wide range pedestal. Under normal conditions SYClRef will be set to 0 and SUVClRef will be set to 128.
DHsel, FidOn, VFilt, UVPol, VSPol, FPol and CCON
* DHsel determines the timing of the HSYNC pulse (burstkey = 0 or HSYNC = 1), for the display part * FidOn enables the field identification position fine tuning; FidOn = 1 takes the value of registers 4FH or 57H; FidOn = 0 takes a hard wired default value * VFilt enhances the vertical reduction filter for vertical reduction modes 13 and 14 * SUVPol and MUVPol invert the UV polarity of the YUV data * DUVPol inverts the UV polarity of the border colours * VSPol determines the active edge of the VSYNC (positive edge is logic 0 and negative edge is logic 1) * FPol can invert the field ID of the incoming fields * CCON enables the clamp correction circuit.
Pedestals
On the acquisition sides YUV can be given an offset during the clamp. Using this mechanism minor offsets in the matrices can be adjusted. The steps are from -8 to +7 with a resolution of 1 LSB of the ADC.
VSPre and VSPost
VSPre is the number of lines before a VSYNC where the PLL is put in free-running mode. VSPost is the number of lines after the VSYNC where the PLL is still free-running. Outside this area the PLL is in normal mode.
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 15 Decoder and PLL settings SUB ADDRESS 12H 13H 14H 15H 16H 17H 20H 21H 22H 23H 24H 25H 29H 2AH REPLAY SETTINGS - - - DHsel IntCOff - - SFidOn MFidOn FbDel(2 : 0) SPedestY(3 : 0) SPedestU(3 : 0) SPedestV(3 : 0) - - VSPre VSPost DATA BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
SAB9079HS
BIT 1
BIT 0
SYClRef(7 : 0) SUClRef(7 : 0) SVClRef(7 : 0) MYClRef(7 : 0) MUClRef(7 : 0) MVClRef(7 : 0) SVFilt MVFilt SUVPol MUVPol DUVPol SVSPol MVSPol SFPol MFPol YDel(2 : 0) MPedestY(3 : 0) MPedestU(3 : 0) MPedestV(3 : 0) SCCON MCCON
RepInc
Repinc is the auto increment used during replay acquisition/display.
DChaOff
DChaOff is the channel offset for the display. It can be used in trick modes or software replay as the channel number to be displayed.
RepAcq, RepDisp, RepCont, DCha+ and DCha-
Bit RepAcq enables the replay acquisition loop, in which pictures are stored with DChaDis as time distance. Bit RepDisp enables the display of stored pictures. When bit RepCont = 1 it enables a continuous looping during display, when bit RepCont = 0 it enables the step function. Bit DCha+ enables one step forward (next picture), bit DCha- enables one step back in time (previous picture). It should be noted that if bits RepAcq and RepDisp are both logic 1 at the same time, the internal display number will be the present acquisition number minus 1.
DChaDis
DChaDis is the number of internal VSYNCs between two stored and/or displayed fields.
RepMax
RepMax is the maximum number of different fields that will be stored in the memory during replay.
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 16 Replay settings SUB ADDRESS 2BH 2CH 2DH 2EH 2FH Note 1. RGBOn enables the YUV to RGB matrix. It is not related to the replay registers. BORDER AND COLOUR SETTINGS Several border and colour settings are given in Table 17. - DCha+ - - DCha- - RepAcq RepDisp DATA BYTES BIT 7 - BIT 6 - BIT 5 BIT 4 BIT 3 BIT 2
SAB9079HS
BIT 1
BIT 0
DChaOff(5 : 0) DChaDis(7 : 0) RepMax(5 : 0) RepCont RepInc(5 : 0) - - RGBOn(1)
Colour registers
The colour registers are all built-up in a similar way: * Bit 6 is the on bit which determines whether the border (or OSD) is visible * Bits 5 and 4 determine the brightness level of the colour (see Table 18) * Bits 2, 1 and 0 determine the colour type (see Table 18) * SB = Sub Border * SBS = Sub Border Select (which PIP has a different border colour) * MB = Main Border * BG = Back Ground * OSD is the OSD character * OSDS = the background of the selected OSD character.
BHSize and BVSize
Bits BHSize and BVSize control the horizontal and vertical border size in steps of 2 pixels and 1 line.
OUVPol
Bit OUVPol sets the UV polarity for all the OSD related colours.
FBLON
If bit FBLON is set to logic 1 the FBL pin is made HIGH under the condition that standard signals are applied. If PAL signals are applied, this function is overruled for the SAB9078HS.
SBSel Shade
Bit Shade gives the OSD characters a shade. The SBSel bits select which sub PIP has a different border colour, if SBSON is set to logic 1. The colour type can be set with SBSBrt and SBSCol.
OSDBLK
Bit OSDBLK blanks all OSD characters but retains their values in memory.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 17 border and colour settings SUB ADDRESS 30H 31H 32H 33H 34H 35H 36H 37H - - - FBLON OUVPol Shade - DATA BYTES BIT 7 BIT 6 SBON SBSON MBON BGON OSDON OSDBLK - BIT 5 BIT 4 BIT 3 - - - - - - BIT 2
SAB9079HS
BIT 1 SBCol(2 : 0) SBSCol(2 : 0) MBCol(2 : 0) BGCol(2 : 0) OSDCol(2 : 0) OSDSCol(2 : 0)
BIT 0
BHSize(3 : 0) SBBrt(1 : 0) SBSBrt(1 : 0) MBBrt(1 : 0) BGBrt(1 : 0) OSDBrt(1 : 0) OSDSBrt(1 : 0) - -
BVSize(3 : 0)
SBSel(3 : 0)
Table 18 Colour registers COLOUR TYPE COLOUR White (low) Blue Red Magenta Green Cyan Yellow White (high) OSD CONTROLS OSD can be placed on the screen in 4 rows of 4 strings. Each string can hold up to 6 characters. They can be placed on top of the sub PIPs. Fine positioning is done with the OSDHfp and OSDVfp bits. The OSDHDis bits determine the distance between the strings and OSDVdis determine the distance between the rows (see Table 19). VALUE 0H 1H 2H 3H 4H 5H 6H 7H 0H 0% 30% 30% 30% 30% 30% 30% 60% BRIGHTNESS LEVELS 1H 10% 50% 50% 50% 50% 50% 50% 70% 2H 30% 70% 70% 70% 70% 70% 70% 80% 3H 50% 100% 100% 100% 100% 100% 100% 100%
OSDEXP
It is possible to expand the OSD characters. 0xH is standard, 10H doubles the size and 11H quadruples the size.
OSDBG and OSDTR
Bit OSDBG sets the OSD background. Bit OSDTR sets the transparency of the OSD background; the options are given in Table 20.
OSDHfp and OSDVfp
Bits OSDHfp and OSDVfp control the fine positioning of the OSD text in steps of 4 pixels and 1 line.
OSDHRep and OSDVRep
Bit OSDHRep (see Table 21) sets the actual number of strings per row (a maximum of 4). Bit OSDVRep sets the actual number of rows (a maximum of 4).
OSDHDis and OSDVDis
Bit OSDHDis determines the distance between the strings (in steps of 4 pixels) and bit OSDVdis determines the distance between the rows (in steps of 1 line).
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 19 OSD control registers SUB ADDRESS 38H 39H 3AH 3BH 3CH OSDEXP OSDBG DATA BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
SAB9079HS
BIT 1
BIT 0
OSDHfp(7 : 0) OSDVfp(7 : 0) OSDHDis(7 : 0) OSDVDis(7 : 0) OSDTR OSDHRep(1 : 0) OSDVRep(1 : 0)
Table 20 OSD background MODE Only OSD OSD with BG Transparent Table 21 Row and string settings OSDXRep VALUE 00B 01B 10B 11B OSD CHARACTERS The OSD characters can be written to I2C-bus sub address 80H and higher (see Table 22). The index OSDCHRpos,row,col indicates the character position in the string, the row number and the column number of the string. Table 22 OSD write register SUB ADDRESS 80H 81H 82H 83H 84H 85H 86H 86H | DEH DFH DATA BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSDHRep NR. OF STRINGS 1 2 3 4 OSDVRep NR. OF ROWS 1 2 3 4 OSDBG 0 1 1 OSDTR x 0 1 PIP (BG) 30% white 50% PIP/30% white NOTE
OSDChr0,0,0 OSDChr0,0,1 OSDChr0,0,2 OSDChr0,0,3 OSDChr0,1,0 OSDChr0,1,1 OSDChr0,1,2 OSDChr0,1,3 | OSDChr5,3,2 OSDChr5,3,3
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
OSDChr
SAB9079HS
The OSDChr byte is divided into groups. The lower 7 bits OSDChr(6 : 0) contain the character to be displayed according to the character ROM table. Bit 7 indicates whether the character is selected, e.g. to change the background of that character. Selecting the first character of a string selects the whole string; selecting any other character has no effect. Table 23 Character ROM table; see also Fig.8 UPPER 3 BITS 0H 1H 2H 3H 4H 5H 6H 7H Note 1. Rows 0H and 1H are not completely represented because of their graphical contents (e.g. a smiley). 0 @ P p ! 1 A Q a q " 2 B R b r
3 4 2 3 1 6 1 4 1 3 1 2 1 1
LOWER 4 BITS 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
# 3 C S c s
$ 4 D T d t
% 5 E U e u
& 6 F V f v
' 7 G W g w
( 8 H X h x
) 9 I Y i y
* : J Z j z
+ ; K [ k {
, < L \ l |
= M ] m }
. > N ^ n ~
/ ? O _ o
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SAB9079HS
handbook, full pagewidth
UPPER 3 BITS
LOWER 4 BITS 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
0H
1H
2H
3H
4H
5H
6H
7H
MGS828
Fig.8 OSD character set.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
YUV TO RGB CONVERSION MATRIX SETTINGS
SAB9079HS
RGBOn
RGBOn enables the YUV to RGB matrix.
XXCoefn (all coefficients)
The YUV to RGB conversion matrix has the following 3 equations: 1. R = RYCoef x Yd + RUCoef x 2 x (Ud - 128) + RVCoef x 2 x (Vd - 128) 2. G = GYCoef x Yd + GUCoef x 2 x (Ud - 128) + GVCoef x 2 x (Vd - 128) 3. B = BYCoef x Yd + BUCoef x 2 x (Ud - 128) + BVCoef x 2 x (Vd - 128) In this equation Yd is normalised for the range 0 to 255, Ud and Vd for the range -128 to 128. The UV coefficients are twos complement in the range -1 coef < 1. The Y coefficients are positives in the range 0 coef < 2. For PAL pictures the coef1 values are used, for NTSC the coef2 values. Table 24 Conversion settings SUB ADDRESS 2EH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH Note 1. DCha+, DCha-, RepAcq, RepDisp and RepCont are used for replay settings. They are not related to the conversion matrix. DATA BYTES BIT 7 DCha+ BIT 6 DCha- BIT 5 RepAcq BIT 4 RepDisp BIT 3 RepCont BIT 2 - BIT 1 - BIT 0 RGBOn
RYCoef1(7 : 0) RUCoef1(7 : 0) RVCoef1(7 : 0) GYCoef1(7 : 0) GUCoef1(7 : 0) GVCoef1(7 : 0) BYCoef1(7 : 0) BUCoef1(7 : 0) BVCoef1(7 : 0) RYCoef2(7 : 0) RUCoef2(7 : 0) RVCoef2(7 : 0) GYCoef2(7 : 0) GUCoef2(7 : 0) GVCoef2(7 : 0) BYCoef2(7 : 0) BUCoef2(7 : 0) BVCoef2(7 : 0)
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
EXTRA DECODER SETTINGS
SAB9079HS
SmlPal
If this bit is set to logic 1, the vertical acquisition and display window for PAL is decreased from 276 lines to 258 lines
ClDel and ClPer
XXClDel sets the delay from the rising edge of the HSYNC/burstkey to the beginning of the internally generated clamp pulse for signal XX in steps of 1 pixel. XXClPer sets the pulse width of the internally generated clamp pulse in steps of 1 pixel.
TGAct1, TGAct2, TColBar, TGenY, TGenU and TGenV
For test purposes, a built-in colour bar/ramp generator is available which replaces the ADC digital output data. This test generator is enabled if TGAct1 and TGAct2 are both set to logic 1, and is disabled when TGAct2 is set to logic 0 (it is recommended to set TGAct1 to logic 1). The test pattern (common for main and sub channels) is set to colour bar if TColBar is set to logic 1 and set to a ramp if TColBar is set to logic 0. Both patterns start at a HSYNC pulse. By use of bit(s) TGenX (active logic 1) the Y, U and V of the pattern can be controlled independently.
FidPos
Bit Fidpos defines the position of the field identification window. The purpose is to set it so that the incoming VSYNC is halfway up the window. This allows a spread of 1 line for the VSYNC (VCR and/or less sophisticated 4 decoder types) in steps of 2 pixels.
VGate
XVGate disables the detection of a next VSYNC for a number of lines, after detecting an initial one in steps of 1 line. Table 25 Extra decoder settings SUB ADDRESS 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH - SmlPal - - TGAct1 - - - - - - - - - - - - - -
DATA BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SYClDel(7 : 0) SUClDel(7 : 0) SVClDel(7 : 0) SYClPer(5 : 0) SUClPer(5 : 0) SVClPer(5 : 0) SFidPos(7 : 0) SVGATE(5 : 0) MYClDel(7 : 0) MUClDel(7 : 0) MVClDel(7 : 0) MYClPer(5 : 0) MUClPer(5 : 0) MVClPer(5 : 0) MFidPos(7 : 0) MVGATE(5 : 0) TGAct2 TColBar TGenY TGenU TGenV
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
DACs These are 8-bit DACs. The maximum output sample frequency is 28 MHz. Acquisition channel ADCs and clamping The analog input signals are converted to digital signals by means of three ADCs. The resolution of the ADCs is 8-bit (DNL is 7-bit, INL is 6-bit) and the sampling is done at the system frequency of 14 MHz. The inputs should be AC-coupled and an internal clamp circuit will clamp the input to Vref(B)(SA/MA) for the luminance channels and to V ref(T)(SA/MA) + V ref(B)(SA/MA) LSB ---------------------------------------------------------------------- + ---------2 2 for the chrominance channels.
SAB9079HS
The clamping starts at the active edge of the internally generated clamp period signal. The clamp period signal, generated from the HSYNC pulse, has a delay adjusted with the XXCICel bits with respect to the HSYNC. Internal video buffers amplify the standard input signals Y*, U and V to the correct ADC levels. The bandwidth of the input signals should be limited to 4.5 MHz for the Y input and 1.125 MHz for the U and V inputs. PLL The PLL generates, from the HSYNC, an internal system clock of 3584 HSYNC which is approximately 56 MHz. The other system clocks are derived from this clock. They are in the range 3584, 1792, 896 or 448 x HSYNC.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD(P) VDDD(C) VDDA Pmax Tstg Tamb VESD PARAMETER digital supply voltage for the peripheral digital supply voltage for the core analog supply voltage maximum power dissipation storage temperature ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model; see "UZW-B0/FQ-B302". 2. Machine model; see "UZW-B0/FQ-A302". QUALITY SPECIFICATION According to "SNW-FQ-611 Part E", dated 14 december 1992. The numbers of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 37 UNIT K/W CONDITIONS MIN. -0.5 -0.5 -0.5 - -25 0 - - MAX. +6.0 +4.0 +4.0 1.5 +150 70 3000 300 V V V W C C V V UNIT
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
ANALOG CHARACTERISTICS VDDD(P) = 5.0 V; VDDD(C) = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD(P)n VDDD(C)n VDDA VSS(n) VDD(max) VSS(max) IDDD(q) IVDDA(MP) IVDDA(SP) IVDDA(MA) IVDDA(SA) IVDDA(DA) IDDA(tot) IDDD(tot) all digital supply voltages for the peripheral all digital supply voltages for the core analog supply voltages all ground voltages maximum difference between supply voltages maximum difference between ground voltages quiescent current of digital supply voltages main PLL analog supply current sub PLL analog supply current main ADCs supply current sub ADCs supply current DACs supply current total analog supply current total digital supply current note 2 note 2 note 3 note 1 4.5 3.0 3.0 - - - - - - - - - - - note 4 note 4 note 5 note 5 note 5 clamping off clamping on; note 2 Ci fs RES DNL INL cs PSRR input capacitance sample frequency resolution differential non-linearity integral non-linearity channel separation power supply rejection ratio note 6 note 2 note 2 note 2 2.65 0.95 - - - - - - - 8 -1.4 -2.0 - - 5.0 3.3 3.3 0 0 0 0 0.4 0.4 78 78 10 170 115 PARAMETER CONDITIONS MIN. TYPE
SAB9079HS
MAX.
UNIT
5.5 3.6 3.6 - 100 100 50 - - 96 96 17 210 - 2.95 1.20 1.04 1.10 1.38 - - - - 8 +1.4 +2.0 - -
V V V V mV mV A mA mA mA mA mA mA mA
Analog-to-digital converter and clamping VVref(T)(SA/MA) top reference voltage VVref(B)(SA/MA) bottom reference voltage ViY(p-p) ViV(p-p) ViU(p-p) Ii input signal amplitude (peak-to-peak value) input signal amplitude (peak-to-peak value) input signal amplitude (peak-to-peak value) input current 2.82 1.08 1.00 1.05 1.33 0.1 55 5 896xHSYNC 8 - - 48 48 V V V V V A A pF kHz bit LSB LSB dB dB
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SYMBOL Vclamp(Y) Vclamp(UV) VVref(T)(DA) VVref(B)(DA) RL CL fs RES DNL INL cs PSRR PARAMETER clamping voltage level Y clamping voltage level UV CONDITIONS note 7 note 8 MIN. 1.25 1.80 TYPE 1.35 1.95
SAB9079HS
MAX. 1.45 2.10 V V
UNIT
Digital-to-analog converter and output stage top reference voltage bottom reference voltage load resistance load capacitance sample frequency resolution differential non-linearity integral non-linearity channel separation power supply rejection ratio note 3 note 3 note 3 note 3 1FH; note 6 2FH; note 6 1.10 0.15 1 0 - - 8 -1.0 -1.0 - - 14 1.20 0.22 - - 1792HSYNC 896HSYNC 8 - - 48 48 1.30 0.30 1000 50 - - 8 +1.0 +1.0 - - 18 V V k pF kHz kHz bit LSB LSB dB dB
Main PLL and clock generation fi(PLL)(main) fi(PLL)(sub) Notes 1. Digital clocks are silent, POR connected to VDD. 2. Load resistance of Vbias(MA)/Vbias(SA) is 39 k. 3. The load resistance of DAC outputs is 1 k. 4. The VVref(T)(SA/MA) and VVref(B)(SA/MA) are made by a resistor division of VDDA. They can be calculated with the formulae: 2V ref(T)(nom) a) V Vref(T)(SA/MA) = V DDA x ------------------------------ V V DDA(nom) V ref(B)(nom) b) V Vref(B)(SA/MA) = V DDA x -------------------------- V V DDA(nom) 5. The input signal is amplified to meet an internal peak-to-peak voltage level of VVref(T)(SA/MA) - VVref(B)(SA/MA). 6. The internal system frequencies are 3584, 1792, 896 and 448 times the HSYNC input frequency. 7. The Y* channel is clamped to the VVref(B)(SA/MA) of the ADCs, which is derived from pin Vref(B)(SA) and pin Vref(B)(MA). 8. The UV channels are clamped to 0.5 x (VVref(T)(SA/MA) + VVref(B)(SA/MA) + VLSB). Where VLSB is one step of the ADC. input frequency 1FH note 6 15.75 kHz
Sub PLL and clock generation input frequency note 6 14 15.75 18 kHz
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
COLOUR PATH CHARACTERISTICS SYMBOL G(conv)(MY) G(conv)(SY) G(conv)(MU) G(conv)(SU) G(conv)(MV) G(conv)(SV) G(conv)(DY) G(conv)(DU) G(conv)(DV) MMADC(Y) MMADC(U) MMADC(V) MMADC(YUV) Note 1. Mismatch = (max - min)/average. PARAMETER analog Y* input ADC conversion gain for main channel analog Y* input ADC conversion gain for sub channel analog U input ADC conversion gain for main channel analog U input ADC conversion gain for sub channel analog V input ADC conversion gain for main channel analog V input ADC conversion gain for sub channel analog Y output ADC conversion gain analog U output ADC conversion gain analog V output ADC conversion gain analog Y ADC mismatch analog U ADC mismatch analog V ADC mismatch analog YUV ADC mismatch note 1 note 1 note 1 note 1 CONDITIONS MIN. 0.20 0.20 0.15 0.15 0.19 0.19 6.0 6.0 6.0 - - - - TYP. 0.22 0.22 0.17 0.17 0.21 0.21 6.8 6.8 6.8 0 0 0 0
SAB9079HS
MAX. 0.24 0.24 0.19 0.19 0.23 0.23 7.5 7.5 7.5 5 5 5 5
UNIT LSB/mV LSB/mV LSB/mV LSB/mV LSB/mV LSB/mV LSB/mV LSB/mV LSB/mV % % % %
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
DIGITAL CHARACTERISTICS All VDDD(C) pins = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL DC characteristics VIH VIL Vhys VOH VOL ILI IOZ Rpu fsys tr tf Note HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage input leakage current 3-state input leakage current internal pull-up resistor VDDD = 3.6 V VDDD = 3.6 V 70 - - VDDD(P) - 0.4 - - - 23 - - - - - 30 - - 0.1 0.2 50 PARAMETER CONDITIONS MIN. TYPE
SAB9079HS
MAX. - 30 - - 0.4 1 1 80
UNIT
%VDDD %VDDD %VDDD V V A A k
AC characteristics system frequency rise time fall time note 1 3584xHSYNC 6 6 25 25 kHz ns ns
1. The internal system frequencies are 3584, 1792, 896 and 448 times the HSYNC input frequency. TEST AND APPLICATION INFORMATION TV application with insertion before 100 Hz feature box (double window) In the 100 Hz application the deflection circuit operates at 100 Hz. The PIP data is inserted into the main decoder output stream and fed to the feature box. The double window feature is made at 1Fh and the field rate is doubled in the feature box. The internal synchronization is illustrated in Fig.9.
handbook, full pagewidth
Y*UV DECODER HV Y*UV HV MAIN AND DISPLAY SUB
Y*UV/RGB FBL
SWITCH DECODER HV
FEATURE BOX
MGS829
Y*UV HV
Fig.9 1Fh/1Fv application with insertion before the feature box.
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SLAVE 2FH GENERAL DESCRIPTION In the slave mode the main and display channel has to follow an external 2Fh, xFv signal. The main acquisition cannot handle such a source, the main/display PLL can. Thus no main channel PIP is available, only the upconverted sub channel can be inserted. The following functions are available in 4 : 1 : 1 only unless otherwise indicated: * Suitable for single PIP, multi PIP, replay and channel overview applications * Data formats 4 : 1 : 1 (all modes) and 4 : 2 : 2 (some modes) * PIP OSD for the sub channels displayed * Detection of PAL/NTSC with overrule bit 2FH, 1FV ALGORITHMS Table 26 Available 2Fh and 1Fv algorithms ALGORITHM progressive scan line doubling Notes FORMAT 4 : 1 : 1 yes yes FORMAT 4 : 2 : 2 no; note 1 yes
SAB9079HS
* CTE and LTE like circuits in display part * Replay with definable auto increment, picture sample rate and picture number auto wrap * Programmable Y*UV to RGB conversion matrix with independent coefficients for NTSC and PAL sources * Display clock and synchronization are derived from the main channel PLL. The following features are only available for the sub channel: * Sample rate of 14 Mhz, 720 Y* pixels/line * Horizontal reduction factors 11 12, 13, 14 and 16 * Vertical reduction factors 11, 12, 13 and 14.
REMARKS proscan (median filtering) note 2
1. Median filtering in 4 : 2 : 2 mode is allowed for single PIP (no main channel) and reduction factors not greater than 1 for both horizontal and vertical 2 2. The performance of the line doubling algorithm is dependent on the picture content. Line (based interlace) flickering will remain in this mode. 2FH, 2FV ALGORITHMS Table 27 Available 2Fh and 2Fv algorithms ALGORITHM AABB field doubling ABAB field doubling AB'A'B fields interpolation via median filtering AB'A'B+ field interpolation via median filtering and averaging with original fields Note 1. Median filtering in 4 : 2 : 2 mode is allowed for single PIP (no main channel) and reduction factors not greater than 1 for both horizontal and vertical 2 FORMAT 4 : 1 : 1 yes yes yes yes FORMAT 4 : 2 : 2 yes yes no; note 1 no; note 1 digital scan digital scan plus REMARKS
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SLAVE 2FH AND XFV RELATED I2C-BUS REGISTERS Table 28 Overview of the I2C-bus registers and their subaddresses SUB ADDRESS 01H 02H DATA BYTES BIT 7 D2FH BIT 6 D2FV BIT 5 - BIT 4 - CTE BIT 3 BIT 2
SAB9079HS
BIT 1 LTE(2:0)
BIT 0
MFld(1:0)
SFld(1:0)
YUVFilter(1:0)
ABMode(1:0)
D2FH and D2FV
These bits control the display mode with respect to 2Fh or 100 Hz features. If D2FH is set to logic 1 the number of lines is doubled and/or if D2FV is set to logic 1 the number of fields is doubled.
ABMode
These bits select the different algorithms for 2Fh modes; see Table 29.
Algorithm selection
Several display algorithms can be set with these bits; an overview is given in Table 29. Note: BGVfp The resolution of the MAVfp bits changes in 2Fh and xFv modes. In 2Fh and 1Fv modes the vertical resolution is 2 lines/field/step on 1Fh base. In 2Fh and 2Fv modes the vertical resolution is 2 lines/field/step on 2Fh base. Table 29 Overview of algorithm selection MODE No filter UV 1 : 1 V filter Y 1 : 1 V filter YUV 1 : 1 V filter 2FH/1FV frame 2FH/1FV proscan 2FH/1FV line doubling not valid 2FH/2FV AABB 2FH/2FV ABAB 2FH/2FV AB'A'B 2FH/2FV AB'A'B+ D2FH 0 0 0 0 1 1 1 1 1 1 1 1 YUVFilter 00H 01H 10H 11H xxH xxH xxH xxH 00H 00H 00H 00H D2FV - 0 0 0 0 0 0 0 1 1 1 1 ABMode 00H 00H 00H 00H 00H 01H 10H 11H 00H 01H 10H 11H
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SLAVE 2FH MEMORY REQUIREMENTS
SAB9079HS
In the slave 2Fh modes only the sub picture can be present. The following conditions must be met: * When vertical reduction is 1, the field mode can be set to 3 * When vertical reduction is not equal to 1, the field mode must be set to 4 * When no live picture is present, such as replay or channel overview, the field mode can be set to 1. Under these conditions a maximum number of stored fields/pictures can be determined. Combined with the size of one picture, the total amount needed can be calculated always supposing that 1 PIP is live. A selected overview is given in Table 30. The VDRAM size is 262144 words of 16 bits Table 30 Memory requirements for 2Fh slave MODE 2 x V1_H2 4 x V2_H2 6 x V2_H3 9 x V3_H3 12 x V4_H3 16 x V4_H4 PICTURES STORED 4 7 9 12 15 19 PICTURE SIZE NTSC (WORDS) 46284 23142 15390 10260 7695 5928 TOTAL NTSC 185136 161994 138510 123120 115425 112632 PICTURE SIZE PAL (WORDS) 56028 28014 18630 12420 9315 7176 TOTAL PAL 224112 196098 167670 149040 139725 136344
SLAVE 2FH DESIGN RESTRICTIONS The design has margins for a 2Fh frequency of 31.5 kHz. Applying a SVGA source with a horizontal frequency of 38 kHz will stress the SAB9079HS. Therefore, a SVGA source can only be applied under the following restricted conditions: * Power supply spread of 5% instead of 10% * No VCR like phase jump in 2Fh signal. Table 31 Design characteristics SYMBOL Supplies VDDD(P) VDDD(C) VDDA VSS fi(PLL) all digital supply voltages for periphery all digital supply voltages for core all analog supply voltages all ground voltages 4.75 3.15 3.15 - note 1 note 2 Note 1. The PLL will lock within 20 lines to instable sources with a large phase jump if the frequency is within the range 28 to 36 kHz. 2. The PLL will lock to stable 2Fh sources with a maximum frequency of 60 kHz. 28 - 5.0 3.3 3.3 0 5.25 3.6 3.6 - 36 60 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Main PLL and clock generation 31.50 - kHz kHz
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
TV APPLICATION WITH INSERTION AFTER 100 HZ (SLAVE)
SAB9079HS
In this application there is no relationship between the deflection and acquisition circuits. A double window feature can be realized by letting the feature box compress one window and make the second window by the SAB9079HS. In this application the HVSYNC of the feature box/line doubler is connected to the main acquisition HVSYNC. The restriction is that no main PIPs can be displayed. The application diagram is illustrated in Fig.10.
handbook, full pagewidth
Y*UV DECODER HV SUB
Y*UV/RGB FBL
Y*UV (not used) HV
DISPLAY
DECODER
HV
FEATURE BOX/ LINE DOUBLER
SWITCH
MGS830
Y*UV HV
Instead of the feature box a SVGA signal can be applied.
Fig.10 2Fh/1Fh application with insertion after the feature box/line doubler.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Master 2Fh general description A 1Fh, 1Fv signal at the acquisition side can be upconverted to a 2Fh, 1Fv or a 2Fh, 2Fv signal. The restriction is that both acquisition channels will be upconverted at the same time.Therefore, the main channel displayed as 1Fh, 1Fv combined with a sub channel displayed as 2Fh, 1Fv is not possible. In the master mode the SAB9079HS generates the HSYNC and VSYNC for display/deflection. There is no protection built in. HSYNC and VSYNC cannot be coupled directly to a tube. A deflection IC should be applied. Both main and sub pictures can be acquired/displayed. The following functions are available: * Suitable for single PIP, some multi PIP modes, replay and channel overview applications * Data formats 4 : 1 : 1 (all modes) and 4 : 2 : 2 (some modes) 2FH, 1FV ALGORITHMS Table 32 Available 2Fh and 1Fv algorithms ALGORITHM progressive scan line doubling Notes FORMAT 4 : 1 : 1 yes yes FORMAT 4 : 2 : 2 no; note 1 yes
SAB9079HS
* Sample rate of 14 Mhz, 720 Y* pixels/line * Horizontal reduction factors for main channel 1 3 , 2 , 1 , 1 , 1 and 1 14 3 2 3 4 6 * Horizontal reduction factors for sub channel 1 3 , 2 , 1 , 1 , 1 and 1 14 3 2 3 4 6 * Vertical reduction factors 11, 12, 13 and 14. * PIP OSD for the sub channels displayed * Detection of PAL/NTSC with overrule bit * CTE and LTE like circuits in display mode * Replay with definable auto increment, picture sample rate and picture number auto wrap * Programmable Y*UV to RGB conversion matrix with independent coefficients for NTSC and PAL sources * Display clock and synchronization are derived from the main channel PLL.
REMARKS proscan (median filtering) note 2
1. Median filtering in 4 : 2 : 2 mode is allowed for single PIP (no main channel) and reduction factors not greater than 1 for both horizontal and vertical 2 2. The performance of the line doubling algorithm is dependent on the picture content. Line (based interlace) flickering will remain in this mode. 2FH, 2FV ALGORITHMS Table 33 Available 2Fh and 2Fv algorithms ALGORITHM AABB field doubling ABAB field doubling AB'A'B fields interpolation via median filtering AB'A'B+ field interpolation via median filtering and averaging with original fields Note 1. Median filtering in 4 : 2 : 2 mode is allowed for single PIP (no main channel) and reduction factors not greater than 1 for both horizontal and vertical 2 FORMAT 4 : 1 : 1 yes yes yes yes FORMAT 4 : 2 : 2 yes yes no; note 1 no; note 1 digital scan digital scan plus REMARKS
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
MASTER 2FH AND XFV RELATED I2C-BUS REGISTERS Table 34 Overview of the I2C-bus registers and their subaddresses SUB ADDRESS 01H 02H 26H 27H 28H DATA BYTES BIT 7 D2FH - - - BIT 6 D2FV - - - - BIT 5 DMaster - BIT 4 DVSPos CTE HSWidth VSDel VSWidth BIT 3 BIT 2
SAB9079HS
BIT 1 LTE(2:0)
BIT 0
MFld(1:0)
SFld(1:0)
YUVFilter(1:0)
ABMode(1:0)
D2FH, D2FV, DMaster and DVSPos
These bits control the display mode with respect to 2Fh or 100 Hz features. If D2FH is set to logic 1 the number of lines is doubled and/or if D2FV is set to logic 1 the number of fields is doubled. If DMaster is at logic 0 the device is in slave mode. DHSYNC and DVSYNC should not be used. If DMaster is at logic 1 the device is in master mode which means that HV synchronization signals are generated. They are derived from MHSYNC and MVSYNC. The DHSYNC and DVSYNC output signals should be used as sync signals for the deflection IC. DVSPos is only valid if DMaster is set to logic 1. If DVSPos is set to logic 0 the VSYNC pulses are generated with an alternating field ID according to the ABAB algorithm. If DVSPos is set to logic 1 the VSYNC pulses are generated in the AABB scheme which means that two first fields are alternated with two second fields.
HSWidth
The width of the DHSYNC can be set in the master mode. The width is from 0 to 31 pixels and the resolution is one 2Fh pixel.
VSWidth
The width of the DVSYNC can be set in the master mode. The scale is from 0 to 31 lines on a 2Fh base and the resolution is 12 2Fh.
VSDel
The position of the DVSYNC, with respect to the incoming MVSYNC, can be set in the master mode. The delay is a 6-bit value and the steps are from 0 to 63 lines on a 2Fh base and the resolution is 12 2Fh line.
Algorithm selection
Several display algorithms can be set with these bits; an overview is given in Table 35. Note: BGVfp The resolution of the BGVfp bits changes in 2Fh and xFv modes. In 2Fh and 1Fv modes the vertical resolution is 2 lines/field/step on 1Fh base. In 2Fh and 2Fv modes the vertical resolution is 2 lines/field/step on 2Fh base.
ABMode
These bits select the different algorithms for 2Fh modes; see Table 35.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Table 35 Overview of algorithm selection MODE No filter UV 1 : 1 V filter Y 1 : 1 V filter YUV 1 : 1 V filter 2FH/1FV frame 2FH/1FV proscan 2FH/1FV line doubling not valid 2FH/2FV AABB 2FH/2FV ABAB 2FH/2FV AB'A'B 2FH/2FV AB'A'B+ FIELD MODE SETTINGS D2FH 0 0 0 0 1 1 1 1 1 1 1 1 YUVFilter 00H 01H 10H 11H xxH xxH xxH xxH 00H 00H 00H 00H D2FV - 0 0 0 0 0 0 0 1 1 1 1
SAB9079HS
ABMode 00H 00H 00H 00H 00H 01H 10H 11H 00H 01H 10H 11H
In the master mode signals will be synchronized to the main 1Fh, 1Fv input signal. This eases the restrictions on the number of fields to be stored for the scan converted main picture. Conditions to be met for a live picture are given in Table 36. Table 36 Master 2Fh field mode settings VERTICAL REDUCTION 1/1 other modes FIELDS FOR MAIN CHANNEL 2 4 FIELDS FOR SUB CHANNEL 3 4 REMARKS except for horizontal reduction 1/1 -
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
FEATURE BOX APPLICATION 100 HZ (MASTER)
SAB9079HS
In this mode the SAB9079HS generates the display clock which is derived from the main clock and synchronization signals. The whole system runs at one PLL. Only full screen images of the main decoder are handled. The PIP insertion of the sub channel is not required here; see Fig.11.
handbook, full pagewidth
Y*UV (not used) SUB HV (not used) Y*UV DECODER HV DISPLAY HV Y*UV/RGB DEFLECTION HV
MGS831
Y*UV
Fig.11 100 Hz application with ECO-100 Hz function.
DOUBLE WINDOW AND/OR OTHER PIP FUNCTIONS AT 100 HZ (MASTER) This is the same configuration as Fig.11 but the sub channel is also needed and, therefore, a second PLL. The constraints apply with respect to the memory use and performance. Double window PAL is only possible if bit SmlPal is set to logic 1, this is due to the memory limitations.
handbook, full pagewidth
Y*UV DECODER HV SUB
Y*UV DECODER HV DISPLAY
Y*UV/RGB HV DEFLECTION
Y*UV HV
MGS832
Fig.12 100 Hz application with 2 channel PIP function.
DOUBLE WINDOW AND/OR OTHER PIP FUNCTIONS AT 2FH, 1FV (MASTER) For the application diagram please refer to Fig.12.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
PACKAGE OUTLINE SQFP128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.72 mm
SAB9079HS
SOT387-3
c
y
X
102 103
65 64
A
e E HE wM bp pin 1 index
128 1 39 38
A
A2 A1 (A 3) Lp L detail X
e
bp D HD
wM B
vM A
vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.40 A1 min. 0.25 A2 2.90 2.50 A3 0.25 bp 0.27 0.17 c 0.23 0.11 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.50 HD HE L Lp 1.03 0.73 v 0.20 w 0.08 y 0.08 7 0
23.35 17.35 1.60 23.05 17.05
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT387-3 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 98-03-27
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
SAB9079HS
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
SAB9079HS
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Preliminary specification
Multistandard Picture-In-Picture (PIP) controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAB9079HS
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2000 Jan 13
47
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/50/01/pp48
Date of release: 2000
Jan 13
Document order number:
9397 750 05258

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